[abc80] abc80 på DE1 (fpga-kort) - henger?

Torfinn Ingolfsen tingox at gmail.com
Mon Aug 10 10:21:33 PDT 2009


On Mon, Aug 10, 2009 at 7:16 PM, H. Peter Anvin <hpa at zytor.com> wrote:

> On 08/10/2009 10:12 AM, Torfinn Ingolfsen wrote:
> >
> > Warning: Implemented PLL "pll1:pll1|altpll:altpll_component|pll" as
> Cyclone
> > II PLL type, but with warnings
> >     Warning: PLL "pll1:pll1|altpll:altpll_component|pll" has the gated
> lock
> > counter value set to 16 which is less than the recommended value of 5000
> > (when inclk[0] has input frequency specified as 50.0 MHz)
> >     Warning: PLL "pll2:pll2|altpll:altpll_component|pll" has the gated
> lock
> > counter value set to 16 which is less than the recommended value of 2400
> > (when inclk[0] has input frequency specified as 24.0 MHz)
>
> Verkar totalt skumt!
>
> Alla inställningar i Quartus ska redan finnas i abc80.qsf-filen...
>

Jeg laster ned Quartus II 8.1 nå, så får vi se om det blir bedre ed den.

-- 
mvh
Torfinn Ingolfsen


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