[abc80] abc80 på DE1 (fpga-kort) - henger?
Torfinn Ingolfsen
tingox at gmail.com
Mon Aug 10 10:12:08 PDT 2009
2009/8/10 Torfinn Ingolfsen <tingox at gmail.com>
>
> Hmm, kanskje jeg skulle forsøke å kompilerer prosjektet med en eldre
> versjon av Quartus enn 9.0sp2?
> Jeg har 7.1, rettelse 7.2 installert - jeg prøver den.
>
Ok, prøvde nå - det gjorde ingen forskjell.
Her er meldingene (warnings) som Quartus 7.2 kom med:
Warning (10463): Verilog HDL Declaration warning at sddisk.v(143): "do" is
SystemVerilog-2005 keyword
Warning (10463): Verilog HDL Declaration warning at keyboard.v(76): "do" is
SystemVerilog-2005 keyword
Warning (10229): Verilog HDL Expression warning at keyboard.v(93): truncated
literal to match 3 bits
Warning (10463): Verilog HDL Declaration warning at abc80.v(1011): "do" is
SystemVerilog-2005 keyword
Warning (10036): Verilog HDL or VHDL warning at abc80.v(479): object
"v24_cts" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at abc80.v(132): truncated
value with size 32 to match size of target (7)
Warning (10230): Verilog HDL assignment warning at abc80.v(187): truncated
value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at abc80.v(191): truncated
value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at abc80.v(196): truncated
value with size 32 to match size of target (10)
Warning (10230): Verilog HDL assignment warning at abc80.v(760): truncated
value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at abc80.v(883): truncated
value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at abc80.v(945): truncated
value with size 32 to match size of target (5)
Warning (10034): Output port "dram_ba[1]" at abc80.v(48) has no driver
Warning (10034): Output port "dram_ba[0]" at abc80.v(48) has no driver
Warning (10034): Output port "dram_ras_n" at abc80.v(49) has no driver
Warning (10034): Output port "dram_cas_n" at abc80.v(50) has no driver
Warning (10034): Output port "dram_cke" at abc80.v(51) has no driver
Warning (10034): Output port "dram_clk" at abc80.v(52) has no driver
Warning (10034): Output port "dram_cs_n" at abc80.v(53) has no driver
Warning (10034): Output port "dram_we_n" at abc80.v(54) has no driver
Warning (10034): Output port "dram_dqm[1]" at abc80.v(55) has no driver
Warning (10034): Output port "dram_dqm[0]" at abc80.v(55) has no driver
Warning (10034): Output port "dram_a[11]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[10]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[9]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[8]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[7]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[6]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[5]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[4]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[3]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[2]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[1]" at abc80.v(56) has no driver
Warning (10034): Output port "dram_a[0]" at abc80.v(56) has no driver
Warning (10230): Verilog HDL assignment warning at display.v(117): truncated
value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at display.v(376): truncated
value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at display.v(379): truncated
value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at display.v(382): truncated
value with size 32 to match size of target (10)
Warning (10036): Verilog HDL or VHDL warning at t80pio.v(58): object
"IORQ_n_old" assigned a value but never read
Warning (10230): Verilog HDL assignment warning at t80pio.v(89): truncated
value with size 32 to match size of target (1)
Warning (10230): Verilog HDL assignment warning at sddisk.v(284): truncated
value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at sddisk.v(285): truncated
value with size 32 to match size of target (9)
Warning (10230): Verilog HDL assignment warning at sddisk.v(397): truncated
value with size 32 to match size of target (6)
Warning (10230): Verilog HDL assignment warning at sddisk.v(431): truncated
value with size 32 to match size of target (3)
Warning (10230): Verilog HDL assignment warning at sddisk.v(523): truncated
value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at sddisk.v(527): truncated
value with size 32 to match size of target (22)
Warning (10230): Verilog HDL assignment warning at printer.v(123): truncated
value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at printer.v(144): truncated
value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at printer.v(146): truncated
value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at printer.v(151): truncated
value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at printer.v(175): truncated
value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at printer.v(182): truncated
value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at printer.v(199): truncated
value with size 9 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at printer.v(217): truncated
value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at printer.v(220): truncated
value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at printer.v(231): truncated
value with size 32 to match size of target (4)
Warning (10230): Verilog HDL assignment warning at debounce.v(39): truncated
value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at debounce.v(46): truncated
value with size 32 to match size of target (16)
Warning (10230): Verilog HDL assignment warning at sound.v(317): truncated
value with size 32 to match size of target (8)
Warning (10230): Verilog HDL assignment warning at sound.v(45): truncated
value with size 32 to match size of target (14)
Warning (10230): Verilog HDL assignment warning at sound.v(47): truncated
value with size 32 to match size of target (14)
Warning (10230): Verilog HDL assignment warning at sound.v(71): truncated
value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at sound.v(74): truncated
value with size 32 to match size of target (14)
Warning (10036): Verilog HDL or VHDL warning at sound.v(148): object "out"
assigned a value but never read
Warning (10230): Verilog HDL assignment warning at sound.v(163): truncated
value with size 32 to match size of target (11)
Warning (10230): Verilog HDL assignment warning at sound.v(203): truncated
value with size 32 to match size of target (14)
Warning (10230): Verilog HDL assignment warning at sound.v(208): truncated
value with size 32 to match size of target (14)
Warning (10230): Verilog HDL assignment warning at i2c.v(75): truncated
value with size 32 to match size of target (2)
Warning (10230): Verilog HDL assignment warning at i2c.v(84): truncated
value with size 32 to match size of target (5)
Warning (10230): Verilog HDL assignment warning at i2c.v(154): truncated
value with size 32 to match size of target (4)
Warning (12020): Port "busrq_n" on the entity instantiation of "cpu" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "ASTB_n" on the entity instantiation of "piob" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "BSTB_n" on the entity instantiation of "piob" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "BSTB_n" on the entity instantiation of "pioa" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "IEI" on the entity instantiation of "pioa" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "address_b" on the entity instantiation of "char_gen"
is connected to a signal of width 12. The formal width of the signal in the
module is 11. Extra bits will be ignored.
Warning (12020): Port "wren_a" on the entity instantiation of "char_gen" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "address_b" on the entity instantiation of "video_ram"
is connected to a signal of width 12. The formal width of the signal in the
module is 11. Extra bits will be ignored.
Warning (12020): Port "wren_a" on the entity instantiation of "video_ram" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "busrq_n" on the entity instantiation of "kbd_cpu" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "int_n" on the entity instantiation of "kbd_cpu" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "nmi_n" on the entity instantiation of "kbd_cpu" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (12020): Port "wait_n" on the entity instantiation of "kbd_cpu" is
connected to a signal of width 32. The formal width of the signal in the
module is 1. Extra bits will be ignored.
Warning (14130): Reduced register "T80se:cpu|T80:u0|BusReq_s" with stuck
data_in port to stuck value GND
Warning (14130): Reduced register "T80se:cpu|T80:u0|BusAck" with stuck
data_in port to stuck value GND
Warning (14130): Reduced register
"sdcontroller:sdcontroller|T80se:sd_cpu|T80:u0|BusReq_s" with stuck data_in
port to stuck value GND
Warning (14130): Reduced register
"sdcontroller:sdcontroller|T80se:sd_cpu|T80:u0|BusAck" with stuck data_in
port to stuck value GND
Warning (14130): Reduced register
"keyboard:keyboard|T80s:kbd_cpu|T80:u0|BusReq_s" with stuck data_in port to
stuck value GND
Warning (14130): Reduced register
"keyboard:keyboard|T80s:kbd_cpu|T80:u0|INT_s" with stuck data_in port to
stuck value GND
Warning (14130): Reduced register
"keyboard:keyboard|T80s:kbd_cpu|T80:u0|BusAck" with stuck data_in port to
stuck value GND
Warning (14130): Reduced register "T80PIO:piob|data_in[7]" with stuck
data_in port to stuck value GND
Warning (14130): Reduced register "T80PIO:piob|data_in[6]" with stuck
data_in port to stuck value VCC
Warning (14130): Reduced register "T80PIO:piob|data_in[5]" with stuck
data_in port to stuck value VCC
Warning (14130): Reduced register "T80PIO:piob|data_in[4]" with stuck
data_in port to stuck value VCC
Warning (14130): Reduced register "T80PIO:piob|data_in[3]" with stuck
data_in port to stuck value VCC
Warning (14130): Reduced register "T80PIO:piob|data_in[1]" with stuck
data_in port to stuck value GND
Warning (14130): Reduced register
"keyboard:keyboard|T80s:kbd_cpu|T80:u0|NMI_s" with stuck data_in port to
stuck value GND
Warning (14130): Reduced register
"keyboard:keyboard|T80s:kbd_cpu|T80:u0|IntCycle" with stuck data_in port to
stuck value GND
Warning (14130): Reduced register
"keyboard:keyboard|T80s:kbd_cpu|T80:u0|NMICycle" with stuck data_in port to
stuck value GND
Warning: The bidir "dram_dq[0]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[1]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[2]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[3]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[4]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[5]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[6]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[7]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[8]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[9]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[10]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[11]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[12]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[13]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[14]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "dram_dq[15]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[0]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[1]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[2]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[3]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[4]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[5]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[6]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[7]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[8]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[9]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[10]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[11]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[12]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[13]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[14]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[15]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[16]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[17]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[18]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[19]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[20]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[21]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[22]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[23]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[24]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[25]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[26]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[27]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[28]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[29]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[30]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[31]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[32]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[33]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[34]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_0[35]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[0]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[1]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[2]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[3]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[4]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[5]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[6]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[7]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[8]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[9]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[10]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[11]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[12]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[13]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[14]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[15]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[16]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[17]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[18]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[19]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[20]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[21]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[22]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[23]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[24]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[25]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[26]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[27]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[28]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[29]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[30]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[31]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[32]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[33]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[34]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "gpio_1[35]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "fl_dq[0]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "fl_dq[1]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "fl_dq[2]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "fl_dq[3]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "fl_dq[4]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "fl_dq[5]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "fl_dq[6]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "fl_dq[7]" has no source; inserted an always disabled
tri-state buffer.
Warning: The bidir "sd_dat0" has no source; inserted an always disabled
tri-state buffer.
Warning: Removing OPNDRN node "keyboard:keyboard|ps2_mclk~3" that feeds
logic
Warning: Removing OPNDRN node "keyboard:keyboard|ps2_mdata~3" that feeds
logic
Warning: Converted presettable and clearable register to equivalent circuits
with latches. Registers power-up to an undefined state, and DEVCLRn places
the registers in an undefined state.
Warning (13310): Register "video_width" converted into equivalent
circuit using register "video_width~_emulated" and latch "video_width~latch"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "fl_oe_n" stuck at GND
Warning (13410): Pin "fl_we_n" stuck at VCC
Warning (13410): Pin "fl_a[20]" stuck at GND
Warning (13410): Pin "fl_a[21]" stuck at GND
Warning (13410): Pin "dram_ba[0]" stuck at GND
Warning (13410): Pin "dram_ba[1]" stuck at GND
Warning (13410): Pin "dram_ras_n" stuck at GND
Warning (13410): Pin "dram_cas_n" stuck at GND
Warning (13410): Pin "dram_cke" stuck at GND
Warning (13410): Pin "dram_clk" stuck at GND
Warning (13410): Pin "dram_cs_n" stuck at GND
Warning (13410): Pin "dram_we_n" stuck at GND
Warning (13410): Pin "dram_dqm[0]" stuck at GND
Warning (13410): Pin "dram_dqm[1]" stuck at GND
Warning (13410): Pin "dram_a[0]" stuck at GND
Warning (13410): Pin "dram_a[1]" stuck at GND
Warning (13410): Pin "dram_a[2]" stuck at GND
Warning (13410): Pin "dram_a[3]" stuck at GND
Warning (13410): Pin "dram_a[4]" stuck at GND
Warning (13410): Pin "dram_a[5]" stuck at GND
Warning (13410): Pin "dram_a[6]" stuck at GND
Warning (13410): Pin "dram_a[7]" stuck at GND
Warning (13410): Pin "dram_a[8]" stuck at GND
Warning (13410): Pin "dram_a[9]" stuck at GND
Warning (13410): Pin "dram_a[10]" stuck at GND
Warning (13410): Pin "dram_a[11]" stuck at GND
Warning: Design contains 5 input pin(s) that do not drive logic
Warning (15610): No output dependent on input pin "clock_24[1]"
Warning (15610): No output dependent on input pin "clock_27[0]"
Warning (15610): No output dependent on input pin "clock_27[1]"
Warning (15610): No output dependent on input pin "ext_clock"
Warning (15610): No output dependent on input pin "aud_adcdat"
Warning: Implemented PLL "pll1:pll1|altpll:altpll_component|pll" as Cyclone
II PLL type, but with warnings
Warning: PLL "pll1:pll1|altpll:altpll_component|pll" has the gated lock
counter value set to 16 which is less than the recommended value of 5000
(when inclk[0] has input frequency specified as 50.0 MHz)
Info: Implementing clock multiplication of 2, clock division of 1, and
phase shift of 0 degrees (0 ps) for pll1:pll1|altpll:altpll_component|_clk0
port
Info: Implementing clock multiplication of 1, clock division of 2, and
phase shift of 0 degrees (0 ps) for pll1:pll1|altpll:altpll_component|_clk1
port
Warning: Implemented PLL "pll2:pll2|altpll:altpll_component|pll" as Cyclone
II PLL type, but with warnings
Warning: PLL "pll2:pll2|altpll:altpll_component|pll" has the gated lock
counter value set to 16 which is less than the recommended value of 2400
(when inclk[0] has input frequency specified as 24.0 MHz)
Info: Implementing clock multiplication of 2, clock division of 3, and
phase shift of 0 degrees (0 ps) for pll2:pll2|altpll:altpll_component|_clk0
port
Warning: Feature LogicLock incremental compilation is not available with
your current license
Warning: Ignored locations or region assignments to the following nodes
Warning: Node "tck" is assigned to location or region, but does not
exist in design
Warning: Node "tcs" is assigned to location or region, but does not
exist in design
Warning: Node "tdi" is assigned to location or region, but does not
exist in design
Warning: Node "tdo" is assigned to location or region, but does not
exist in design
Warning: Found 257 output pins without output pin load capacitance
assignment
Info: Pin "aud_xck" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "aud_bclk" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sd_clk" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[8]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[9]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[10]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[11]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[12]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[13]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[14]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dq[15]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[8]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[9]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[10]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[11]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[12]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[13]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[14]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[15]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[16]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[17]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[18]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[19]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[20]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[21]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[22]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[23]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[24]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[25]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[26]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[27]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[28]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[29]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[30]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[31]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[32]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[33]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[34]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_0[35]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[8]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[9]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[10]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[11]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[12]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[13]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[14]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[15]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[16]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[17]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[18]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[19]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[20]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[21]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[22]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[23]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[24]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[25]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[26]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[27]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[28]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[29]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[30]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[31]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[32]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[33]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[34]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "gpio_1[35]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ps2_clk" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ps2_dat" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_dq[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_dq[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_dq[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_dq[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_dq[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_dq[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_dq[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_dq[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[8]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[9]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[10]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[11]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[12]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[13]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[14]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_dq[15]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sd_cmd" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sd_dat0" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sd_dat3" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "i2c_scl" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "i2c_sda" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[8]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledr[9]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledg[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledg[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledg[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledg[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledg[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledg[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledg[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "ledg[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_0[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_0[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_0[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_0[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_0[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_0[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_0[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_1[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_1[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_1[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_1[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_1[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_1[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_1[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_2[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_2[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_2[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_2[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_2[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_2[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_2[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_3[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_3[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_3[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_3[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_3[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_3[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "s7_3[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_rst_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_ce_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_oe_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_we_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[8]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[9]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[10]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[11]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[12]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[13]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[14]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[15]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[16]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[17]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[18]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[19]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[20]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "fl_a[21]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_ba[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_ba[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_ras_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_cas_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_cke" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_clk" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_cs_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_we_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dqm[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_dqm[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[8]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[9]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[10]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "dram_a[11]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_ce_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_oe_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_we_n" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_be_n[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_be_n[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[4]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[5]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[6]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[7]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[8]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[9]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[10]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[11]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[12]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[13]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[14]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[15]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[16]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "sram_a[17]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "uart_txd" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_r[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_r[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_r[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_r[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_g[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_g[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_g[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_g[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_b[0]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_b[1]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_b[2]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_b[3]" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_hs" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "vga_vs" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "aud_dacdat" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "aud_daclrck" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Info: Pin "aud_adclrck" has no specified output pin load capacitance --
assuming default load capacitance of 0 pF for timing analysis
Warning: Following 97 pins have no output enable or a GND or VCC output
enable - later changes to this connectivity may change fitting results
Info: Pin dram_dq[0] has a permanently disabled output enable
Info: Pin dram_dq[1] has a permanently disabled output enable
Info: Pin dram_dq[2] has a permanently disabled output enable
Info: Pin dram_dq[3] has a permanently disabled output enable
Info: Pin dram_dq[4] has a permanently disabled output enable
Info: Pin dram_dq[5] has a permanently disabled output enable
Info: Pin dram_dq[6] has a permanently disabled output enable
Info: Pin dram_dq[7] has a permanently disabled output enable
Info: Pin dram_dq[8] has a permanently disabled output enable
Info: Pin dram_dq[9] has a permanently disabled output enable
Info: Pin dram_dq[10] has a permanently disabled output enable
Info: Pin dram_dq[11] has a permanently disabled output enable
Info: Pin dram_dq[12] has a permanently disabled output enable
Info: Pin dram_dq[13] has a permanently disabled output enable
Info: Pin dram_dq[14] has a permanently disabled output enable
Info: Pin dram_dq[15] has a permanently disabled output enable
Info: Pin gpio_0[0] has a permanently disabled output enable
Info: Pin gpio_0[1] has a permanently disabled output enable
Info: Pin gpio_0[2] has a permanently disabled output enable
Info: Pin gpio_0[3] has a permanently disabled output enable
Info: Pin gpio_0[4] has a permanently disabled output enable
Info: Pin gpio_0[5] has a permanently disabled output enable
Info: Pin gpio_0[6] has a permanently disabled output enable
Info: Pin gpio_0[7] has a permanently disabled output enable
Info: Pin gpio_0[8] has a permanently disabled output enable
Info: Pin gpio_0[9] has a permanently disabled output enable
Info: Pin gpio_0[10] has a permanently disabled output enable
Info: Pin gpio_0[11] has a permanently disabled output enable
Info: Pin gpio_0[12] has a permanently disabled output enable
Info: Pin gpio_0[13] has a permanently disabled output enable
Info: Pin gpio_0[14] has a permanently disabled output enable
Info: Pin gpio_0[15] has a permanently disabled output enable
Info: Pin gpio_0[16] has a permanently disabled output enable
Info: Pin gpio_0[17] has a permanently disabled output enable
Info: Pin gpio_0[18] has a permanently disabled output enable
Info: Pin gpio_0[19] has a permanently disabled output enable
Info: Pin gpio_0[20] has a permanently disabled output enable
Info: Pin gpio_0[21] has a permanently disabled output enable
Info: Pin gpio_0[22] has a permanently disabled output enable
Info: Pin gpio_0[23] has a permanently disabled output enable
Info: Pin gpio_0[24] has a permanently disabled output enable
Info: Pin gpio_0[25] has a permanently disabled output enable
Info: Pin gpio_0[26] has a permanently disabled output enable
Info: Pin gpio_0[27] has a permanently disabled output enable
Info: Pin gpio_0[28] has a permanently disabled output enable
Info: Pin gpio_0[29] has a permanently disabled output enable
Info: Pin gpio_0[30] has a permanently disabled output enable
Info: Pin gpio_0[31] has a permanently disabled output enable
Info: Pin gpio_0[32] has a permanently disabled output enable
Info: Pin gpio_0[33] has a permanently disabled output enable
Info: Pin gpio_0[34] has a permanently disabled output enable
Info: Pin gpio_0[35] has a permanently disabled output enable
Info: Pin gpio_1[0] has a permanently disabled output enable
Info: Pin gpio_1[1] has a permanently disabled output enable
Info: Pin gpio_1[2] has a permanently disabled output enable
Info: Pin gpio_1[3] has a permanently disabled output enable
Info: Pin gpio_1[4] has a permanently disabled output enable
Info: Pin gpio_1[5] has a permanently disabled output enable
Info: Pin gpio_1[6] has a permanently disabled output enable
Info: Pin gpio_1[7] has a permanently disabled output enable
Info: Pin gpio_1[8] has a permanently disabled output enable
Info: Pin gpio_1[9] has a permanently disabled output enable
Info: Pin gpio_1[10] has a permanently disabled output enable
Info: Pin gpio_1[11] has a permanently disabled output enable
Info: Pin gpio_1[12] has a permanently disabled output enable
Info: Pin gpio_1[13] has a permanently disabled output enable
Info: Pin gpio_1[14] has a permanently disabled output enable
Info: Pin gpio_1[15] has a permanently disabled output enable
Info: Pin gpio_1[16] has a permanently disabled output enable
Info: Pin gpio_1[17] has a permanently disabled output enable
Info: Pin gpio_1[18] has a permanently disabled output enable
Info: Pin gpio_1[19] has a permanently disabled output enable
Info: Pin gpio_1[20] has a permanently disabled output enable
Info: Pin gpio_1[21] has a permanently disabled output enable
Info: Pin gpio_1[22] has a permanently disabled output enable
Info: Pin gpio_1[23] has a permanently disabled output enable
Info: Pin gpio_1[24] has a permanently disabled output enable
Info: Pin gpio_1[25] has a permanently disabled output enable
Info: Pin gpio_1[26] has a permanently disabled output enable
Info: Pin gpio_1[27] has a permanently disabled output enable
Info: Pin gpio_1[28] has a permanently disabled output enable
Info: Pin gpio_1[29] has a permanently disabled output enable
Info: Pin gpio_1[30] has a permanently disabled output enable
Info: Pin gpio_1[31] has a permanently disabled output enable
Info: Pin gpio_1[32] has a permanently disabled output enable
Info: Pin gpio_1[33] has a permanently disabled output enable
Info: Pin gpio_1[34] has a permanently disabled output enable
Info: Pin gpio_1[35] has a permanently disabled output enable
Info: Pin fl_dq[0] has a permanently disabled output enable
Info: Pin fl_dq[1] has a permanently disabled output enable
Info: Pin fl_dq[2] has a permanently disabled output enable
Info: Pin fl_dq[3] has a permanently disabled output enable
Info: Pin fl_dq[4] has a permanently disabled output enable
Info: Pin fl_dq[5] has a permanently disabled output enable
Info: Pin fl_dq[6] has a permanently disabled output enable
Info: Pin fl_dq[7] has a permanently disabled output enable
Info: Pin sd_dat0 has a permanently disabled output enable
Warning: Following 123 pins have nothing, GND, or VCC driving datain port --
changes to this connectivity may change fitting results
Info: Pin dram_dq[0] has VCC driving its datain port
Info: Pin dram_dq[1] has VCC driving its datain port
Info: Pin dram_dq[2] has VCC driving its datain port
Info: Pin dram_dq[3] has VCC driving its datain port
Info: Pin dram_dq[4] has VCC driving its datain port
Info: Pin dram_dq[5] has VCC driving its datain port
Info: Pin dram_dq[6] has VCC driving its datain port
Info: Pin dram_dq[7] has VCC driving its datain port
Info: Pin dram_dq[8] has VCC driving its datain port
Info: Pin dram_dq[9] has VCC driving its datain port
Info: Pin dram_dq[10] has VCC driving its datain port
Info: Pin dram_dq[11] has VCC driving its datain port
Info: Pin dram_dq[12] has VCC driving its datain port
Info: Pin dram_dq[13] has VCC driving its datain port
Info: Pin dram_dq[14] has VCC driving its datain port
Info: Pin dram_dq[15] has VCC driving its datain port
Info: Pin gpio_0[0] has VCC driving its datain port
Info: Pin gpio_0[1] has VCC driving its datain port
Info: Pin gpio_0[2] has VCC driving its datain port
Info: Pin gpio_0[3] has VCC driving its datain port
Info: Pin gpio_0[4] has VCC driving its datain port
Info: Pin gpio_0[5] has VCC driving its datain port
Info: Pin gpio_0[6] has VCC driving its datain port
Info: Pin gpio_0[7] has VCC driving its datain port
Info: Pin gpio_0[8] has VCC driving its datain port
Info: Pin gpio_0[9] has VCC driving its datain port
Info: Pin gpio_0[10] has VCC driving its datain port
Info: Pin gpio_0[11] has VCC driving its datain port
Info: Pin gpio_0[12] has VCC driving its datain port
Info: Pin gpio_0[13] has VCC driving its datain port
Info: Pin gpio_0[14] has VCC driving its datain port
Info: Pin gpio_0[15] has VCC driving its datain port
Info: Pin gpio_0[16] has VCC driving its datain port
Info: Pin gpio_0[17] has VCC driving its datain port
Info: Pin gpio_0[18] has VCC driving its datain port
Info: Pin gpio_0[19] has VCC driving its datain port
Info: Pin gpio_0[20] has VCC driving its datain port
Info: Pin gpio_0[21] has VCC driving its datain port
Info: Pin gpio_0[22] has VCC driving its datain port
Info: Pin gpio_0[23] has VCC driving its datain port
Info: Pin gpio_0[24] has VCC driving its datain port
Info: Pin gpio_0[25] has VCC driving its datain port
Info: Pin gpio_0[26] has VCC driving its datain port
Info: Pin gpio_0[27] has VCC driving its datain port
Info: Pin gpio_0[28] has VCC driving its datain port
Info: Pin gpio_0[29] has VCC driving its datain port
Info: Pin gpio_0[30] has VCC driving its datain port
Info: Pin gpio_0[31] has VCC driving its datain port
Info: Pin gpio_0[32] has VCC driving its datain port
Info: Pin gpio_0[33] has VCC driving its datain port
Info: Pin gpio_0[34] has VCC driving its datain port
Info: Pin gpio_0[35] has VCC driving its datain port
Info: Pin gpio_1[0] has VCC driving its datain port
Info: Pin gpio_1[1] has VCC driving its datain port
Info: Pin gpio_1[2] has VCC driving its datain port
Info: Pin gpio_1[3] has VCC driving its datain port
Info: Pin gpio_1[4] has VCC driving its datain port
Info: Pin gpio_1[5] has VCC driving its datain port
Info: Pin gpio_1[6] has VCC driving its datain port
Info: Pin gpio_1[7] has VCC driving its datain port
Info: Pin gpio_1[8] has VCC driving its datain port
Info: Pin gpio_1[9] has VCC driving its datain port
Info: Pin gpio_1[10] has VCC driving its datain port
Info: Pin gpio_1[11] has VCC driving its datain port
Info: Pin gpio_1[12] has VCC driving its datain port
Info: Pin gpio_1[13] has VCC driving its datain port
Info: Pin gpio_1[14] has VCC driving its datain port
Info: Pin gpio_1[15] has VCC driving its datain port
Info: Pin gpio_1[16] has VCC driving its datain port
Info: Pin gpio_1[17] has VCC driving its datain port
Info: Pin gpio_1[18] has VCC driving its datain port
Info: Pin gpio_1[19] has VCC driving its datain port
Info: Pin gpio_1[20] has VCC driving its datain port
Info: Pin gpio_1[21] has VCC driving its datain port
Info: Pin gpio_1[22] has VCC driving its datain port
Info: Pin gpio_1[23] has VCC driving its datain port
Info: Pin gpio_1[24] has VCC driving its datain port
Info: Pin gpio_1[25] has VCC driving its datain port
Info: Pin gpio_1[26] has VCC driving its datain port
Info: Pin gpio_1[27] has VCC driving its datain port
Info: Pin gpio_1[28] has VCC driving its datain port
Info: Pin gpio_1[29] has VCC driving its datain port
Info: Pin gpio_1[30] has VCC driving its datain port
Info: Pin gpio_1[31] has VCC driving its datain port
Info: Pin gpio_1[32] has VCC driving its datain port
Info: Pin gpio_1[33] has VCC driving its datain port
Info: Pin gpio_1[34] has VCC driving its datain port
Info: Pin gpio_1[35] has VCC driving its datain port
Info: Pin fl_dq[0] has VCC driving its datain port
Info: Pin fl_dq[1] has VCC driving its datain port
Info: Pin fl_dq[2] has VCC driving its datain port
Info: Pin fl_dq[3] has VCC driving its datain port
Info: Pin fl_dq[4] has VCC driving its datain port
Info: Pin fl_dq[5] has VCC driving its datain port
Info: Pin fl_dq[6] has VCC driving its datain port
Info: Pin fl_dq[7] has VCC driving its datain port
Info: Pin sd_dat0 has VCC driving its datain port
Info: Pin fl_oe_n has GND driving its datain port
Info: Pin fl_we_n has VCC driving its datain port
Info: Pin fl_a[20] has GND driving its datain port
Info: Pin fl_a[21] has GND driving its datain port
Info: Pin dram_ba[0] has GND driving its datain port
Info: Pin dram_ba[1] has GND driving its datain port
Info: Pin dram_ras_n has GND driving its datain port
Info: Pin dram_cas_n has GND driving its datain port
Info: Pin dram_cke has GND driving its datain port
Info: Pin dram_clk has GND driving its datain port
Info: Pin dram_cs_n has GND driving its datain port
Info: Pin dram_we_n has GND driving its datain port
Info: Pin dram_dqm[0] has GND driving its datain port
Info: Pin dram_dqm[1] has GND driving its datain port
Info: Pin dram_a[0] has GND driving its datain port
Info: Pin dram_a[1] has GND driving its datain port
Info: Pin dram_a[2] has GND driving its datain port
Info: Pin dram_a[3] has GND driving its datain port
Info: Pin dram_a[4] has GND driving its datain port
Info: Pin dram_a[5] has GND driving its datain port
Info: Pin dram_a[6] has GND driving its datain port
Info: Pin dram_a[7] has GND driving its datain port
Info: Pin dram_a[8] has GND driving its datain port
Info: Pin dram_a[9] has GND driving its datain port
Info: Pin dram_a[10] has GND driving its datain port
Info: Pin dram_a[11] has GND driving its datain port
Må man gjøre noen spesielle innstillinger i Quartus for at dette prosjektet
skal virke?
--
mvh
Torfinn Ingolfsen
More information about the ABC80
mailing list